september 2012 ? 2009 fairchild semiconductor corporation www.fairchildsemi.com ft7521 ? rev. 1.0.7 ft7521 ? reset timer with fixed delay and reset pulse ft7521 reset timer with fixed delay and reset pulse features ? fixed reset delay: 7.5 seconds ? one input reset pin ? open-drain output pin with fixed 400ms pulse ? 1.8 v to 5.0 v operation (t a =-40c to +85c) ? 1.7 v to 5.0 v operation (t a =-25c to +85c) ? 1.65 v to 5.00 v operation (t a =0c to +85c) ? <1 a i ccq consumption ? zero-second test-mode enable ? integrated pull-up resistor on /sro applications ? cell phones ? portable media players ? tablets ? mobile devices ? consumer medical description the ft7521 is a timer for resetting a mobile device where long reset times are needed. the long delay helps avoid unintended resets caused by accidental key presses. it has a fixed delay of 7.5 20% seconds. the dsr pin enables test mode operation by immediately forcing /rst1 low for factory testing. the ft7521 has one input for single-button resetting capability. the device has a single open-drain output with 0.5 ma pull-down drive. ft7521 draws minimal i cc current when inactive and functions over a power supply range of 1.65 v to 5.0 v. figure 1. block diagram ordering information part number operating temperature range package packing method FT7521L6X -40 ? c to +85 ? c 6-lead, micropak? 1.0 x 1.45 mm, jedec mo-252 5000 units on tape and reel ft7521fhx (preliminary) 6-lead, micropak2? 1.0 x 1.0 mm body, .35 mm pitch
? 2009 fairchild semiconductor corporation www.fairchildsemi.com ft7521 ? rev. 1.0.7 2 ft7521 ? reset timer with fixed delay and reset pulse recommended application diagram figure 2. recommended application diagram pin configuration figure 3. pad assignments (top-through view) pin definitions pin # name description normal operation zero-second factory-test mode 1 /rst1 open-drain output, active low open-drain output, active low 2 gnd gnd gnd 3 /sr0 reset input with integrated pull-up, active low reset input with int egrated pull-up, active low 4 vcc power supply power supply 5 dsr delay selection input; tie to gnd during normal operation. (1) delay selection input. pull high to enable zero- second delay for factory test. 6 test used for device testing; tie to gnd during normal operation. used for device testing; tie to gnd during normal operation. note: 1. this pin must always be tied to either gnd or vcc. it must not float.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com ft7521 ? rev. 1.0.7 3 ft7521 ? reset timer with fixed delay and reset pulse absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter condition min. max. unit v cc supply voltage -0.5 7.0 v v in dc input voltage /sr0, dsr -0.5 7.0 v v out output voltage (2) /rst1 -0.5 7.0 v i ik dc input diode current v in < 0v -50 ma i ok dc output diode current v out < 0v -50 ma i ol dc output sink current +50 ma i cc dc v cc or ground current per supply pin ? 100 ma t stg storage temperature range -65 +150 ? c t j junction temperature under bias +150 ? c t l junction lead temperature, soldering 10 seconds +260 ? c p d power dissipation 5 mw esd electrostatic discharge capability human body model, jesd22-a114 4 kv charged device model, jesd22-c101 2 note: 2. all output current absolute maximum ratings must be observed. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificatio ns. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter condition min. max. unit v cc supply voltage (3) -40 ? c to +85 ? c 1.8 5.0 v -25 ? c to +85 ? c 1.7 5.0 0 ? c to +85 ? c 1.65 5.00 t rfc v cc recovery time after power down v cc =0 v after power down, rising to 0.5 v 5 ms v in input voltage (3) /sr0 0 5 v v out output voltage /rst1 0 5 v i ol dc output sink current /rst1, v cc =1.8 v to 5.0 v +3 ma t a free-air operating temperature -40 +85 ? c ? ja thermal resistance 350 c/w note: 3. v cc supply should never be allowed to float while input pins are driven.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com ft7521 ? rev. 1.0.7 4 ft7521 ? reset timer with fixed delay and reset pulse dc electrical char acteristics conditions of t a =-40 to 80c with v cc =1.8 - 5.0 v or t a =-25 to 85c with v cc =1.7 ? 5 v or t a =0 to 85c with v cc =1.65 ? 5 v produce the perfo rmance characteristics below. symbol parameter condition min. typ. max. unit v ih input high voltage dsr, /sr0 0.65 x v cc v v il input low voltage dsr, /sr0 0.25 x v cc v v ol low level output voltage rst, i ol =500 a 0.3 v rst, i ol =3 ma, v cc =3.0 v 0.3 r pu integrated pull-up resistor on /sr0 50 k ? i in input leakage current /sr0 v in = v cc ? 1.0 a input leakage current dsr 0v ? v in ? 5.0 v ? 1.0 i cc quiescent supply current (timer inactive) /sr0=v cc 1 a dynamic supply current (timer active) /sr0=0 v 200 ac electrical characteristics conditions of t a =-40 to 80c with v cc =1.8 - 5.0 v or t a =-25 to 85c with v cc =1.7 ? 5 v or t a =0 to 85c with v cc =1.65 ? 5 v produce the perfo rmance characteristics below. symbol parameter condition min. typ. max. unit t phl1 timer delay, /sr0 to rst (dsr=0) c l =5 pf, r l =5 k ? , see figure 4 6.0 7.5 9.0 s t rec reset timeout delay 320 400 480 ms capacitance specifications t a =+25 ? c. symbol parameter condition typ. unit c in input capacitance v cc =gnd 4 pf c out output capacitance v cc =5.0 v 5 pf
? 2009 fairchild semiconductor corporation www.fairchildsemi.com ft7521 ? rev. 1.0.7 5 ft7521 ? reset timer with fixed delay and reset pulse functional description default operation time n is 7.5 s. if the dsr pin is pulled high prior to v cc ramp, the ft7521 enters test mode and the reset output, /rst1, is immediately pulled low for factory testing. the dsr pin must be forced to gnd during normal operation. the dsr pin should never be driven high or left to float during normal operation. the dsr pin stat e should never be changed during device operation; it must be biased prior to supplying the v cc supply. if there is a need to use the dsr=vcc test mode, the /sr0 must be high when the dsr pin is moved from low to high to enter zero- second factory-test mode. to return to the standard 7.5-second reset time, the same procedure must be followed with dsr=gnd. the dsr pin should never be allowed to change state while the /sr0 pin is low. the vcc supply pin should never be left to float while other input pins are driven. if the vcc pin is allowed to float, care should be taken to ensur e that /sr0 is not driven to any voltage greater than gnd. operation modes a low input signal on /sr0 starts the oscillator. there are two scenarios for counting: short duration and long duration. in the short-durat ion scenario, output /rst1 is not affected. in the long-d uration scenario, the output /rst1 goes low after /sr0 has been held low for ? 7.5 s. the /rst1 output returns to its original high state 400ms after time t rec has expired, regardless of the state of /sr0. the /r st1 output is an open-drain driver. when the count time exceeds time 7.5 s, the /rst1 output pulls low. short duration (t w < 7.5 s) when the /sr0 input goes low, the internal timer starts counting. if the /sr0 input goes high before 7.5 s has elapsed, the timer stops counting and resets and no changes occur on the outputs. long duration (t w > 7.5 s) when the /sr0 input goes low, the internal timer starts counting. if the /sr0 input stays low for at least 7.5 s, the rst output is enabled and pu lled low. the output rst is held low for t rec , 400 ms, as soon as the reset time of 7.5 s is met, regardless of the state of the /sr0 pin. when the /sr0 input has returned high and the t rec has expired, the internal timer resets and awaits the next reset event. zero-second test mode /rst1 goes low immediately after /sr0 goes low. figure 4. reset timing waveforms
? 2009 fairchild semiconductor corporation www.fairchildsemi.com ft7521 ? rev. 1.0.7 6 ft7521 ? reset timer with fixed delay and reset pulse ac test circuit and waveforms figure 5. ac test circuit and waveforms for /rst1 output st output
? 2009 fairchild semiconductor corporation www.fairchildsemi.com ft7521 ? rev. 1.0.7 7 ft7521 ? reset timer with fixed delay and reset pulse physical dimensions figure 6. 6-lead, micropak? 1.0 x 1.45 mm, jedec mo-252 package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . 2. dimensions are in millimeters 1. conforms to jedec standard m0-252 variation uaad 4. filename and revision: mac06arev4 notes: 3. drawing conforms to asme y14.5m-1994 top view recommened land pattern bottom view 1.45 1.00 a b 0.05 c 0.05 c 2x 2x 0.55max 0.05 c (0.49) (1) (0.75) (0.52) (0.30) 6x 1x 6x pin 1 detail a 0.075 x 45 chamfer 0.25 0.15 0.35 0.25 0.40 0.30 0.5 (0.05) 1.0 5x detail a pin 1 termina l 0.40 0.30 0.45 0.35 0.10 0.00 0.10 cba 0.05 c c 0.05 c 0.05 0.00 5x 5x 6x (0.13) 4x 6x pin 1 identifier (0.254) 5. pin one identifier is 2x length of any 5 other line in the mark code layout.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com ft7521 ? rev. 1.0.7 8 ft7521 ? reset timer with fixed delay and reset pulse physical dimensions figure 7. 6-lead, micropak2? 1.0 x 1.0 mm body, .35 mm pitch package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . 1.00 b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994 notes: a. complies to jedec mo-252 standard 0.05 c a b 0.55max 0.05 c c 0.35 0.09 0.19 123 0.35 0.25 5x 6x detail a 0.60 (0.08) 4x (0.05) 6x 0.40 0.30 0.075x45 chamfer 5x 0.40 0.35 1x 0.45 6x 0.19 top view bottom view 0.66 0.10 cba .05 c 0.89 pin 1 0.05 c 2x 2x 1.00 d. landpattern recommendation is based on fsc e. drawing filename and revision: mgf06arev3 0.52 0.73 0.57 0.20 6x 1x 5x recommended land pattern for space constrained pcb detail a pin 1 lead scale: 2x alternative land pattern for universal application design. 0.90 min 250um 65 4 0.35 (0.08) 4x side view
? 2009 fairchild semiconductor corporation www.fairchildsemi.com ft7521 ? rev. 1.0.7 9 ft7521 ? reset timer with fixed delay and reset pulse
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